This invention relates generally to nanowire devices and methods for forming such devices.
Semiconductor devices are subject to ever-more-stringent size constraints. The development of improved device architectures to meet these constraints is a constant challenge. In response to this challenge, devices based on semiconductor nanowires are currently under development. These “nanowires” are elongate, thin (sub-micron) wires which can be formed from semiconductors using lithographic processing or growth techniques. Nanowires generally have a thickness of up to about 200 nm, and more usually nearer 50 nm, with thicknesses from about 2 nm to about 50 nm being most typical at present. The cross-sectional shape of nanowires can vary, common examples including rounded (e.g., circular) cross-sections as well as generally rectangular cross-sections giving a ribbon-shaped nanowire or “nanoribbon”. Nanowires may be embodied in a variety of devices in microelectronic circuitry, a common application in MOS (metal oxide semiconductor) technology being as the channel structure of FET (field effect transistor) devices. Nanowire FETs can exploit a “surround-gate” arrangement in which the gate stack is formed as a generally cylindrical structure surrounding the nanowire channel.
In planar MOS technology, strained silicon has been used to increase the carrier mobility in the channel of FETs. The basic process here is illustrated in FIGS. 1a to 1d of the accompanying drawings. A layer of SixGe1-x is initially grown as illustrated schematically in FIGS. 1a and 1b. Since germanium has a larger lattice constant (5.65.ANG.) than silicon (5.4.ANG.), the resulting crystal structure is larger. In a subsequently-grown silicon layer as indicated in FIG. 1c, the silicon atoms try to align according to the expanded SiGe lattice. The SiGe base layer thus serves as a stressor for the overlaid silicon layer. As a result, the final silicon layer is in tensile strain (ΔL/L>0, where L represents length parallel to the surface) as illustrated in FIG. 1d. To produce the final transistor structure as illustrated schematically in FIG. 2, the gate stack is completed by overlaying the strained silicon with a gate dielectric and gate electrode.
A planar silicon layer can also be subjected to strain by thermal oxidation, the volume being enlarged by the incorporated oxygen atoms so that the Si surface atoms are in tensile strain. Silicon nitride has also been used as a stressor layer on top of the gate in some planar transistor architectures to induce strain in the silicon channel.
In nanowire geometry, a strained Si channel can be realized by providing a SiGe core and growing a strained Si shell around that core. A gate stack and source and drain contacts on the ends of the nanowire complete the strained Si MOS gate-all-around transistor. The current in the channel of such a transistor flows in the strained Si and the SiGe does not contribute to current flow. U.S. Patent Application publication No. U.S.2008/0276979 discloses strained nanowires for thermoelectric applications in which quantum dots arranged in anti-phase on opposite surfaces of a nanoribbon induce a periodic surface strain modulation resulting in anti-correlated positional displacement of the ribbon along its length.